In a lateral junction field effect transistor, which may also be referred to as a “lateral JFET” hereinafter, a gate electrode applies a reverse bias voltage to a pn junction located on a side of a channel region, through which carriers pass, so that a depletion layer stretches from the pn junction into the channel region. Thereby, a conductance of the channel region is controlled to perform operations such as switching. Particularly, the lateral JFET is configured to move the carriers parallel to an element surface in the channel region.
The carriers in the channel may be either electrons (n-type) or holes (p-type). However, the JFET having a semiconductor substrate made of SiC usually employs a channel region formed of an n-type impurity region in many cases. For the sake of illustration, therefore, it is assumed in the following description that carriers in a channel are electrons, and thus a channel region is formed of an n-type impurity region. Naturally, the channel region may be formed of a p-type impurity region.
FIG. 72 is a cross section showing a conventional lateral JFET (U.S. Pat. No. 5,264,713, “Junction Field Effect Transistor in Silicon Carbide”). A p+-type epitaxial layer 112 is arranged on an n-type SiC substrate 110, and an n−-type channel layer 114 is arranged on epitaxial layer 112. On one and the other portions of channel layer 114 located on opposite sides of a trench 124, an n+-type source region 116 and an n+-type drain region 118 are arranged, respectively. Source and drain electrodes 120 and 122 are arranged on source and drain regions 116 and 118, respectively. A gate contact layer 130 is formed on a rear surface of SiC substrate 110, and a gate electrode (not shown) is arranged on gate contact layer 130. Trench 124 located between source/drain regions 116 and 118 extends into channel layer 114. A channel C is formed in a portion of epitaxial layer 114 of a second conductivity type located between trench 124 and epitaxial layer 112 of the first conductivity type.
Epitaxial layer 112 is doped with p-type impurities more heavily than epitaxial layer 114 including the channel and doped with n-type impurities, and therefore is configured such that the reverse bias voltage applied to the junction portion enlarges the depletion layer toward the channel. When the depletion layer fills the channel, a current cannot pass through the channel so that an off state is attained. Therefore, a magnitude of the reverse bias voltage can be controlled to fill the channel region with the depletion layer filling, and not to fill it. Thereby, by controlling, e.g., the reverse bias voltage between the gate and source, it is possible to control on/off of the current.
Further, “Theory of Semiconductor Superjunction Devices” (Jpn. J. Appl. Phys. Vol. 36 (1997) Part 1, No. 10 Octover 1997, pp. 6254–6262) theoretically describes as follows. A structure (superimposed junction structure) including p- and n-type semiconductor layers superimposed together is employed between a channel and a drain of an MOS field effect transistor so that distribution of a voltage applied to a drain in the off state may be similar to that of a parallel plane plate capacitor. Thereby, it is possible to improve a breakdown voltage of an element, and at the same time, it is possible to suppress increase of an on-resistance of the element, or to lower the on-resistance.
In the lateral JFET having the foregoing structures, however, it has been required to lower the on-resistance as one of factors for improving characteristics. Particularly, it is strongly desired in the lateral JFET of the normally-off type to lower the on-resistance.
In the structure shown in FIG. 72, however, if a space between the top of p+-type epitaxial layer 112 and the bottom of gate contact layer 130 is increased in expectation of lowering of the on-resistance, this increases an absolute value of the gate voltage required for turn-off. Therefore, the above space can be increased only to a limited extent, and the on-resistance can be lowered only to a limited extent.
In the normally-off type, the space must be smaller than a space for the depletion layer extended by a diffused potential in a junction between channel layer 114 and gate contact layer 130, and therefore can be increased only to a limited extent so that the on-resistance can be lowered only to a limited extent.